In contemporary microprocessors, the size of embedded static random access memories (SRAMs) almost doubles every generation. Embedded SRAMs may provide better performance than off die memory. Large embedded SRAMs are typically designed using a small-signal approach (as compared to a full-swing approach) in order to maximize density. Unfortunately, a delay of a small-signal SRAM does not scale as well as a delay that of full-swing logic (like a register file). In the latter case, the delay is a function of the supply voltage (Vcc), which scales with technology.
In contrast, SRAM delay depends on a time that it takes a small memory cell to develop a sufficient differential voltage on a bitline. This differential voltage should be larger than an offset of a Sense-Amplifier (SA) used to convert the small differential input to a full-swing output. The SA offset may depend on random process variations, which tends to worsen with feature size scaling. Furthermore, sub-threshold leakage current, which roughly triples every generation, may add to the differential requirements. These factors make it difficult for the read access time to scale. Accordingly, additional circuit/architectural techniques are used to maintain cycle scaling.